Advances in semiconductor technology have been accompanied by continuous improvement in miniaturization of semiconductor components such as MOS transistors, leading to increasingly stringent standards for gate oxide thickness and quality. A key objective for semiconductor manufacturers in this regard is the development of ultra-thin gate dielectric layer that is high in quality, reliability, durability, and that offers high voltage and resistance.
Dynamic random access memory (DRAM) is an illustrative example of a key integrated circuit enjoying rapid advancement through persistent research and development. A DRAM cell generally includes a transistor and a capacitor controlled by the transistor, and the transistor includes at least one gate structure having a gate dielectric layer such as a silicon oxide layer.
An undesired side effect of component miniaturization has resulted from thinning of the gate dielectric layer, which has led to leakage and reduced reliability.
A traditional method of reducing leakage is to increase the thickness of the gate dielectric layer, or to implant nitrogen into the gate dielectric layer to increase the dielectric constant (K). For example, for a silicon oxide layer having a dielectric constant of 4, a nitrogen-implanted silicon oxide layer can increase the dielectric constant to 8.
A traditional soak rapid thermal process (RTP) is performed at 400-1150° C. for about 20 seconds to stabilize the nitrogen in the gate dielectric layer. However, nitrogen can diffuse into the gate dielectric layer after the “long-term” rapid thermal process. Besides, other “long-term” rapid thermal processes, such as for forming gate layer and source/drain, will further increase the diffusion of nitrogen. The conventional rapid thermal processes can degrade the capacitive effective thickness (CET) and reduce reliability.
Therefore, there is need for methods of fabricating a gate dielectric layer and fabricating a gate structure.